1. Field of the Invention
The present invention is related to current-switched digital to analog converters.
2. Background Art
An analog section of digital-to-analog converters (DACs) usually receives complementary drive signals that are generated using a switch driver circuit. The switch driver circuit receives digital signals and generates the drive signals therefrom. The analog section uses the received drive signals to generate analog signals representative of the digital signals.
Ideally, the drive signals have rise and fall times that are substantially equal (e.g., a rise time of a first drive signal is substantially equal to a fall time of a second drive signal, and vice versa). This is because matching of the rise and fall times of the drive signals is critical to linearity performance of the DAC circuit, especially when a high speed sampling clock is required. Therefore, mismatches of the rise and fall times of the drive signals should be kept as small as possible. However, conflicts between elements in the switch driver circuit typically result in some mismatch between rise and fall times of the drive signals, which often results in a mismatch that is above threshold level.
Therefore, what is needed is a system and method that generate drive signals having rise and fall times that are substantially equal.